Superjunction device and process for its manufacture

ABSTRACT

A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

RELATED APPLICATION

[0001] This application is based on and claims benefit of U.S.Provisional Application No. 60/394,037, filed Jul. 3, 2002 and U.S.Provisional Application No. 60/442,316, filed Jan. 22, 2003 to which aclaim of priority is hereby made.

FIELD OF THE INVENTION

[0002] This invention relates to MOSgated devices and more specificallyrelates to a novel superjunction type MOSgated device and processes forits manufacture.

BACKGROUND OF THE INVENTION

[0003] Superjunction devices are well known and normally employ greatlydeepened spaced base regions or pedestals of one conductivity disposedin a drift region of the other conductivity. By balancing the charge ofthe deep bases to that of the drift layer so that they deplete oneanother when the device is in a blocking condition, it is possible touse a higher concentration for drift region, resulting in reduced onresistance during forward conduction of the device.

[0004] A major problem in superjunction devices is in the formation ofthe ultra-deep base region. Thus, a large number of epitaxial layerswith respective base implants, mask layers, implants and diffusions aresequentially formed. The large number of process steps cause the devicesto be very expensive. It would be desirable to provide a process with areduced number of mask steps for the manufacture of a superjunctiondevice.

BRIEF DESCRIPTION OF THE INVENTION

[0005] In accordance with the invention, a superjunction device is madeparticularly for lower voltage ranges, less than about 200 volts, inwhich a high concentration P implant layer (for an N channel device) isburied in the central portion of the depth of the epitaxial junctionreceiving layer and is then heated to cause it to expand upward anddownward to form a pedestal type structure. A plurality of spacedpedestals of this kind are formed. Thereafter, a conventional MOSgatedstructure is formed atop each pedestals.

[0006] In a first embodiment of the invention, a first epitaxial layeris grown atop a substrate and spaced P type implants are applied to thesurface of the first N type epitaxial layer. A second N type epitaxiallayer of about the same thickness as the first is then grown atop thefirst layer and the spaced P type implants. The number of P type dopantcharges is made about equal to the number of N type charges in the Ntype epi layers surrounding each pedestal. The two layer device is thenheated, causing the implants to diffuse upward and downward, forming theplural P type posts or pedestals the N type epitaxial layers. Aconventional MOSgated structure is then formed atop each of thepedestals, completing the device.

[0007] In a second embodiment of the invention, for example, for under100 volt devices, a single epitaxial layer may be used, and a very highenergy implant, for example 3 MeV, can implant boron or other atoms inthe mid depth of the epitaxial layer. These are then vertically expandedby diffusion to form the desired pedestals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a cross-section of a small portion of a silicon waferand shows the formation of a first epitaxial layer and the formation ofimplanted P regions on the upper surface of the first epitaxial layer.

[0009]FIG. 2 shows the structure of FIG. 1 after the deposition of asecond epitaxial layer.

[0010]FIG. 3 shows the structure of FIG. 2 after diffusion to drive theimplants upward and downward.

[0011]FIG. 4 shows the structure of FIG. 3 after the formation of aconventional MOSgate structure atop each of the pedestals of FIG. 3.

[0012]FIG. 5 shows the electric field distribution in the structure ofFIG. 4 (in dotted lines) compared to that of a prior art structure.

[0013]FIG. 6 shows a second embodiment of the invention in which highenergy implants form implants in the central depth of a single epitaxiallayer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Referring first to FIG. 1, a conventional N⁺ silicon substrate 10(a P substrate would be used for a P channel MOSFET) first has an N⁻epitaxial layer 11 grown thereon. For a 200 volt device, layer 11 mayhave a resistivity of about 1.5 ohm cm and a thickness of about 6microns, the thickness and resistivity depending on the desired reversevoltage withstand of the devices being made.

[0015] The top surface of layer 11 is then masked with a suitable mask12 having windows 13, 14 at locations corresponding to the locationsdesired for P type pedestals in an N⁻ drift region. A boron implant, forexample, at 50 KeV and a dose of about 1E13 per cm² is then applied toareas exposed by windows 13 and 14, shown as implants 15 and 16. Theseare not critical values.

[0016] The mask 12 is then striped away and a second epitaxial layer 20(FIG. 2) of thickness and resistivity, which may be the same as those oflayer 11, is grown atop layer 11 and implants 15, 16.

[0017] The wafer is next heated in a diffusion chamber, at a suitabletemperature and time to cause the implants 15 and 16 to expand upwardand downward by for example, about 2 to 4 microns in each direction,forming P type pedestals 25, 26 through a major portion of the thicknessof epitaxial layers 11 and 20 as shown in FIG. 3.

[0018] Thereafter a conventional MOSgate structure is formed atop layer20 as shown in FIG. 4. This MOSgate structure includes P type channelregions 30 and 31 which are aligned with and merge into pedestals 25 and26 respectively. The MOSgated structure also includes the conventionalgate oxide 25, polysilicon gate 36, oxide insulation layer (LTO) 37 andsource electrode 38. A drain electrode 39 is formed on the bottom ofsubstrate 10.

[0019] Thus, pedestals 25 and 26 are stacks with opposite doping typefrom that of the epi layers 11 and 20 and of same doping type as channelareas 30 and 31. The total number of dopants (charges) in the pedestalsis equal or close to the total number of dopant (charges) in the epilayers surrounding the pedestals in the style of conventionalSuperjunction devices so that the epi layers can be fully depletedduring reverse voltage operation. The pedestals can extend all the wayto the bottom of epi layer 11, depending on the desired trade-offrelation of breakdown voltage and R_(DSON). The lateral width of thepedestals can also vary for the same trade-off relation. The sameconcept is also applicable to a lateral device, and to devices formed inother semiconductor substrates than silicon.

[0020] By adding pedestals 25 and 26 to the traditional MOSFETstructure, the electrical field distribution from the top to the bottomof the device is changed from a triangle shape (solid line in FIG. 5) toa rectangle shape (the dotted line in FIG. 5), i.e., the electricalfield is uniformly distributed through the device. Thus, a low voltagematerial 11, 20 with higher dopant concentration can be used tofabricate high voltage device without concern of maximum depletiondepth. Typically, this new concept can reduce the R_(DSON) of a MOSFETby more than 65%.

[0021] The same concept described above can also be applied to evenlower voltage devices as shown in FIG. 6. In a traditional lateraldevice, the starting material epi thickness is relatively thin,typically less than 15 μm. With this type of thin epi material, a singlehigh energy implantation method can be used to form the pedestalsdescribed above. One advantage of using implantation over a second epideposition is that implantation usually can have a much better controlof dose, which gives a tighter distribution on breakdown voltage andR_(DSON) of the final product. Another advantage of using implantationin the process is simpler processors and the cycle time is shorter,making the whole process more manufacturable.

[0022] Thus, as shown in FIG. 6, a single epitaxial layer 50 about 6microns thick is grown atop substrate 10, for a lower voltage device,for example, 100 volts. A mask 55 with windows 56 and 57 at locations atthe desired pedestal locations is then formed. A boron implant is thencarried out at a very high energy, for example, 3 MeV and a dose ofabout 1E13 deposits boron implants 60, 61 about midway in the depth oflayer 50. Thereafter, a diffusion is carried out to drive the implantsupward and downward (as shown in dotted lines) to form the desiredpedestals 62 and 63 respectively.

[0023] Thereafter, the MOSgated structure is formed as shown in FIG. 4to complete the device.

[0024] Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein.

What is claimed is:
 1. The process for the manufacture of a substratefor a superjunction device, said process comprising the steps of:forming a first epitaxial semiconductor layer of a given thickness andof a given impurity concentration of a first conductivity type atop asupport body forming a plurality of spaced implants of a secondconductivity type on the surface of said first epitaxial layer; forminga second epitaxial layer of a given thickness and of a givenconcentration and of said first conductivity type atop said first layer;and thereafter heating said substrate and said implants to cause saidimplants to diffuse downwardly into said first layer and upwardly intosaid second layer, thereby forming spaced pedestals of said secondconductivity type within said first and second layers; the total chargeof each of said pedestals being approximately equal to the total chargein the volume of said first and second layers which surrounds saidpedestals.
 2. The process of claim 1, in which said first and secondlayers are silicon.
 3. The process of claim 1, wherein said first andsecond layers are of the same thickness and impurity concentration. 4.The process of claim 2, wherein said support body is a silicon wafer. 5.The process of claim 4, wherein said first and second layers are of thesame thickness and concentration.
 6. The process of claim 4, whereinsaid silicon wafer has the same conductivity type as said first andsecond layers.
 7. The process for the manufacture of a superjunctiondevice comprising the steps of: forming a first epitaxial semiconductorlayer of a given thickness and of a given impurity concentration of afirst conductivity type atop a support body; forming a plurality ofspaced implants of a second conductivity type on the surface of saidfirst epitaxial layer; forming a second epitaxial layer of a giventhickness and of a given concentration and of said first concentrationtype atop said first layer; heating said substrate and said implants tocause said implants to diffuse downwardly into said first layer andupwardly into said second layer, thereby forming spaced pedestals ofsaid second conductivity type within said first and second layers; thetotal charge of each of said pedestals being approximately equal to thetotal charge of the volume of said first and second layers whichsurrounds said pedestals; and thereafter forming MOSgated cell elementsatop each of said pedestals.
 8. The process of claim 7, which furtherincludes forming a drain electrode on the bottom of said support layer,and separating said support layer and said MOSgated cell elements intoseparate unitary elements.
 9. The process of claim 7, wherein saidsupport body is a silicon wafer.
 10. The process of claim 9, whereinsaid silicon wafer has the same conductivity type as said first andsecond layers.
 11. The process of manufacture of a substrate wafer forthe manufacture of superjunction devices, comprising the steps ofdepositing an epitaxial layer of semiconductor material of oneconductivity type atop a support wafer; forming a plurality of laterallyspaced implants of the second conductivity type at vertically interiorlocations of said epitaxial layer; and thermally diffusing said implantsto cause them to diffuse for a given distance upwardly and downwardlywithin said epitaxial layer, thereby to form laterally spacedsuperjunction pedestals within said epitaxial layer; the total charge ofsaid second conductivity type within each of said pedestals being atleast approximately matched to the total charge of the firstconductivity type of said epitaxial layers which surrounds each of saidpedestals.
 12. The process of claim 11, wherein said implants are formedat the approximate mid-point of the thickness of said epitaxial layer.13. The process of claim 12, wherein said epitaxial layer consists offirst and second sequentially formed layers.
 14. The process of claim11, wherein said epitaxial layer and said support wafer are silicon. 15.The process of claim 12, wherein said epitaxial layer and said supportwafer are silicon.
 16. The process of claim 13, wherein said epitaxiallayer and said support wafer are silicon.
 17. The process for themanufacture of a semiconductor device which includes the steps ofdepositing an epitaxial layer of semiconductor material of oneconductivity type atop a support wafer; forming a plurality of laterallyspaced implants of the second conductivity type at vertically interiorlocations of said epitaxial layer; and thermally diffusing said implantsto cause them to diffuse for a given distance upwardly and downwardlywithin said epitaxial layer, thereby to form laterally spacedsuperjunction pedestals within said epitaxial layer; the total charge ofsaid second conductivity type within each of said pedestals being atleast approximately matched to the total charge of the firstconductivity of said epitaxial layers which surrounds each of saidpedestals and thereafter forming MOSgated cell elements atop each ofsaid cell elements.